The ever increasing density of input/output (I/O) connections required between an integrated circuit (IC) chip and its next level packaging in microelectronic systems has rendered the industry increasingly turning to an C4 (controlled collapse chip connections) interconnection technology, which uses solder bumps or solder balls to electrically and mechanically connect the chip I/O pads to pads on a next level of packaging. At the same time, to achieve better performance with reduced power consumption, reduced power dissipation and smaller footprint, the industry also increasingly adopts a three dimensional (3D) integrated circuit. The 3D integrated circuit is manufactured by stacking silicon wafers and/or dies and interconnecting them vertically using through-silicon vias (TSVs) so that they behave as a single device. Both C4 solder bumps and TSVs require electrical testing to ensure their electrical performance and reliability.
Cobra probes have been commonly used in testing of the IC devices containing an area with an array of C4 bumps or similar electrical contacts. A cobra probe normally comprises a plurality of wires (pins) which are mounted in parallel with their respective ends terminating in two planes which extend transversely of the axes of the probe wires. The wires are preshaped and flexible, which fulfills two of the numerous requirements to render them highly successful in probing silicon device wafers. In addition, cobra probes have less force required and thus less damage to the device being tested. Recently, very low force, fine pitch test probes are being developed but have many challenges to overcome. The processes used to manufacture these probes are expensive which makes it even more challenging to reduce the rising test costs expected for 3D and 2.5D integration. While these new probes further extend the ability to test more I/O's, finer pitches, and smaller features, they will again hit road blocks for testing future 3D designs with exploding power and signal connections. Also, 3D wafer to wafer manufacturing features which will shrink beyond the physical and mechanical capability of these new probes. New test probes will likely be limited to 40-50 μm pitch and 20-25 μm test pads. Also, even though they may be able to achieve very low forces below 1 g with minimal damage, they may not be usable in more sensitive processes such as wafer to wafer where any wafer surface disruption can affect the process. In some cases there may be no product test pads available but it may be beneficial to have them to monitor small process variations earlier in the process. As technologies continue to scale, these small variations effecting product are getting more difficult or near impossible to detect with process defect monitors (PDMs). Therefore, there is a need to provide a new method which can address these issues during the C4 manufacturing process or any electrically tested level process, such as testing TSVs for interposer manufacturing process.
Current test solutions allow for assessment of TSV leakage, but do not provide capacity to test for opens. Manufacturing process monitors which include connected TSV chains can be used to monitor a process for opens, shorts, and proximity effects to devices. However, due to the very small critical area of these monitors and lack of unique product design sensitivities to the process, these monitors traditionally become ineffective for product health of the line (HOL) and yield monitoring.
Product known good die (KGD) test is required during high volume manufacturing. DC and AC limited yield problems can cause large product wafer yield loss at significant cost when the problem is discovered during manufacturing final assembly and test steps. A much larger cost is the interruption in the product supply chain followed by the very large costs and fab capacity required for new wafer starts to make up for the product wafers lost. KGD testing for product also requires testing for AC performance and reliability fail mechanisms. Typically these types of fail modes are more difficult to detect and generally are tested for much later in the product assembly process. The only way to guarantee product KGD is to AC test the product critical performance paths. Temporary connections of these paths allow for such testing much earlier in the manufacturing process at any selected wafer level. This has become even more critical due to 3D, 2.5D, and package scaling which limits or eliminates assembly rework processes further impacting cost and yield. These connections enable 100% KGD test coverage for both tester methods and on chip DFT methods.
Current solutions at any wafer test level, including product wafer final test, are also challenged to provide 100% KGD testing due to smaller test interface features, tighter pitches, and exploding I/O interfaces expected to run at high speeds. This effects both KGD yield, but also drives higher test costs and new test development. Current on chip at speed test methods are being discussed but cannot measure through the TSV path. For 2.5D interposers or 3D designs, chip design for test (DFT) features like built in self test (BIST) or DC and AC I/O wrap can now be activated to do more effective I/O wrap tests which include the entire TSV path. In addition, testing a new design earlier in the process provides a means for early user hardware design verification. Designs can then be fixed more quickly during the initial development of a program. Lastly, manufacturing tools Key Performance Indicators (KPI) can be better monitored such as a degradation in a membrane sealing system for copper plating. In this case, the time between plating and a final level test step can cause large volumes of wafer yield loss and/or tool contamination or tool damage impacting production due to tool down time. Therefore, there is a need to provide a process which can form temporary electrical connections between TSVs which will enable electrical testing of TSVs in the early stage of the process during 3D manufacturing.
Tseng et al., in U.S. Pat. No. 8,680,882, teach a method of making an interposer for a 3D IC by providing with a plurality of functional metal wiring segments where the plurality of functional metal wiring segments are connected in series by a plurality of dummy metal wiring segments thus allowing the plurality of functional metal wiring segments to be electrically tested for continuity. Each of the plurality of dummy metal wiring segments is provided with a laser fuse portion for disconnecting the dummy metal wiring segments upon completion of the electrical test. Tseng et al. discuss how to deposit a permanent structure onto a substrate that will later be disconnected electrically but will still remain with the package and the pads themselves. This leads to reliability issues during assembly and consumes the very space that the fine pitch provides.
Hou et al., in U.S. Pat. No. 8,993,432, teach a method and an apparatus for testing the electrical characteristics, such as electrical continuity. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs, also called TSVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be tested by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV. Although the conductive layer may be temporary, the probe test is still carried out on the TVs not on the temporary conductive layer, it does not address many issues associated with the electrical testing described above. Therefore, there is a need to provide a temporary test structure which can address these issues for testing TSVs during interposer fabrication.